The delay associated with a circuit implemented using partially depleted silicon on insulator (PD-SOI) technology is dependent on its switching history. When a circuit first switches after sitting idle for a few milliseconds (ms) or more it will have a longer or shorter delay than when it switches again within a few nanoseconds (ns). The first switch of the circuit is referred to herein as 1SW, while the second switch is referred to herein as 2SW. The fractional difference of the 1SW and 2SW delays, 1SW/2SW history, can be as much as 10% or more, and can be either positive with 2SW faster, or negative with 1SW faster.
This behavior derives from the floating body of PD-SOI, whose potential directly modulates Metal Oxide Semi-Conductor Field Effect Transistor (MOSFET) threshold voltage (Vt) and is influenced by temperature, operational voltage (VDD), leakage currents, and capacitance. This history effect must be taken into account when gauging technology performance as measured, for example, with ring oscillators. It also impacts specific designs where the relative timing of different paths within a circuit is critical. In addition, the same mechanism that modulates delay also impacts Static Random Access Memory (SRAM) margins, as described in, for example, Brian L. Ji, Hussein I. Hanafi, and Mark B. Ketchen, “On the Connection of SRAM Cell Stability with Switching History in Partially Depleted SOI Technology,” Proceedings of the 2006 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2006), Shainghai, China, Oct. 23-26, 2006, pp. 788-791, the disclosure of which is incorporated by reference herein.
If the same circuit is switching on a regular basis, every few nanoseconds (ns) or less, it will have a third delay characteristic of steady state operation, referred to herein as SS. SS delay, as measured with a ring oscillator, typically lies somewhere between the 1SW and 2SW delays. The time it takes for a circuit to achieve this steady state is referred to as a floating body relaxation time or a floating body time constant.
Thus, floating body effects in PD-SOI technology introduce switching delay history into the gate delay of logic gates and erode margins of SRAM cells and other memory elements. Evaluation of such effects has typically involved high speed bench tests in an off-line setting. Recently, structures have been demonstrated for measuring some components of switching delay history using only direct current (DC) inputs and outputs, such as those described in Dale J. Pearson, Mark B. Ketchen and Manjul Bhushan, “Technique for rapid, in-line characterization of switching history in partially depleted SOI technologies,” 2004 IEEE International SOI Conference Proceedings, pp. 148-150, 2004, the disclosure of which is incorporated by reference herein. While these structures provide valuable information on the size of the history, they do not provide any information on the floating body relaxation time.
Floating body relaxation time is a very important parameter for determining impact such as on SRAM margins, where the impact on a given SRAM cell will be a function of the time between successive operations of the cell. Presently the measurement of such time constants remains entirely in the regime of high-speed bench tests, such as those described in Mark B. Ketchen, Manjul Bhushan, and Carl Anderson, “Circuit and Technique for Characterizing Switching Delay History Effects in Silicon on Insulator Logic Gates,” Review of Scientific Instruments, Vol. 75, No. 2, pp. 768-771, 2004, the disclosure of which is incorporated by reference herein.
It is thus of considerable interest and value to develop a test structure that allows one to routinely measure the floating body time constant as an inline test with only DC inputs and outputs.